TLB simulator and effective access time

Problem

Simulate a fully associative TLB with LRU replacement.

Input: entries pageSize tlbNs memNs levels, then logical addresses until the end of input.

For each address, compute its page; a TLB hit if the page is in the TLB (it becomes most recently used), otherwise a miss (insert it, evicting the least recently used entry if the TLB is full).

Print Trace: MHHH… (one letter per access), Hits: h/n, hit ratio X% (one decimal), and EAT: Y ns (no TLB: Z ns) with one decimal, where a hit costs tlb + mem and a miss costs tlb + (levels + 1) × mem; "no TLB" costs (levels + 1) × mem.

Your solution

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