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Chapter 9 · Week 10

Memory Management: From Address Spaces to Paging

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Q1

Base register = 14000, limit register = 3000. The process accesses logical address 346. What happens?

Q2

Same registers (base 14000, limit 3000). The process accesses logical address 3500. What happens?

Q3

Why do modern systems bind addresses at execution time rather than at compile time?

Q4

Holes (in address order): [0, 200), [250, 350), [400, 700), [750, 1000). A request of 90 KB arrives. Where does best fit place it?

Q5

Same holes, same 90 KB request. Where does worst fit place it?

Q6

Total free memory is 210 KB, but a 200 KB request fails because the largest hole is 100 KB. What is this called?

Q7

A 70 KB request is served with a 128 KB block. What is the 58 KB of unused space called?

Q8

Page size is 1,024 bytes. Logical address 5000 has which page number and offset?

Q9

Page size 1,024 bytes; page 7 is in frame 1. What is the physical address of logical address 7700?

Q10

With 32-bit logical addresses and 4 KiB pages, how many bits are used for the offset and for the page number?

Q11

32-bit addresses, 4 KiB pages, 4-byte page-table entries. How large is a single-level page table per process?

Q12

48-bit virtual addresses, 4 KiB pages, 8-byte entries, and each level's table must fit in one page. How many levels are needed?

Q13

TLB lookup 1 ns, memory access 100 ns, 4-level page tables, TLB hit ratio 99 %. What is the effective access time?

Q14

Why is the TLB hit ratio typically very high even though the TLB holds only a few hundred entries?

Q15

What is the main benefit of huge pages (2 MiB instead of 4 KiB)?

Q16

An inverted page table has:

Q17

Which bit in a page-table entry tells the OS that a page has been modified and must be written back before its frame is reused?

Q18

Which statement about segmentation vs. paging is correct?

Q19

Buddy system with 1,024 KB of memory and a 64 KB minimum block. A 70 KB request arrives in empty memory. How many splits are performed, and what block size is used?

Q20

In the buddy system, a block of size 128 starts at address 256. What is the address of its buddy?

Q21

A Kubernetes pod shows status OOMKilled (exit code 137). What happened?

Q22

A 7-billion-parameter model is stored with 16-bit (2-byte) weights. Approximately how much memory do the weights need?

Q23

Why can shared libraries (e.g., libc.so) save a lot of physical memory?

Q24

On a context switch, why can TLB entries be kept if the TLB supports ASIDs/PCIDs?

Q25

Holes (in address order): [0, 200), [250, 350), [400, 700), [750, 1000). The last allocated block ended at address 750. Where does next fit place a 90 KB request?

Q26

What does compaction require, and why is it rarely used for main memory today?

Q27

Linux reports free = 0.8 GiB but available = 10 GiB on a 16 GiB server. Should the operator add RAM?

Q28 Short answer

A system has 16-bit logical addresses and 1 KiB pages. The page table of process P is: page 0 → frame 5, page 1 → not present, page 2 → frame 2, page 3 → frame 7, page 4 → not present, page 5 → frame 0, page 6 → frame 3, page 7 → frame 1 (pages 8 and above are outside P's address space). Translate the logical addresses 0, 1023, 1024, 2100, 5000, 7700 and 9000.

Q29 Short answer

Compute the effective access time for (a) no TLB with 4-level page tables; (b) a TLB with hit ratio 75 %; (c) hit ratio 99 %. Use TLB lookup 1 ns and memory access 100 ns. Then (d) explain what a TLB hit ratio of 75 % suggests about the program, and one way to improve it.

Q30 Short answer

EdgeCampus has an edge board with 8 GB of RAM (the OS and runtime use 1.5 GB) and wants to run a vision model (300 M parameters, 16-bit) and a language model (3 B parameters). Compute the memory needed for the weights of each model at 16-bit and at 4-bit precision, decide what fits simultaneously, and explain how this affects the offloading decision.